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motorola semiconductor technical data ? motorola, inc. 2004 order this document by MPC9894/d preliminary information rev 2 quad input redundant idcs clock generator the MPC9894 is a differential input and output, pll-based intelligent dynamic clock switch (idcs) and clock generator specifically designed for redundant clock distribution systems. the device receives up to four lvpecl clock signals and gene rates eight phase-ali gned output clocks. the MPC9894 is able to detect failing clock signals and to dynamically switch to a redundant clock signal. the switch from the failing clock to the redundant clock occurs without interruption of the output clock signal (output clock slews to alignment). the phase bump typically caused by a clock failure is eliminat- ed. the device offers eight low-skew cl ock outputs organized into four output banks, each configurable to support the different clock frequencies. the ex- tended temperature range of the MPC9894 supports telecommunication and networking requirements. features ? 8 differential lvpecl output pairs quad-redundancy reference clock inputs idcs-on-chip intelligen t dynamic clock switch smooth output phase transiti on during clock failover switch automatically detects clock failures clock activity monitor clock qualifier inputs manual clock select and automatic switch modes 21.25 ? 340 mhz output frequency range specified frequency and phase slew rate on clock switch lvcmos compatible control inputs and outputs external feedback enables zero-delay configurations output enable/disable and st atic test mode (pll bypass) low-skew characteristics: maximum 50 ps1 output-to-output i 2 c interface for device configuration low cycle-to-cycle and period jitter ieee 1149.1 jtag interface 100-ball mapbga package supports 2.5 v or 3.3 v supplies with 2.5 v and 3.3 v i/o junction temperature range -40 c to +110 c functional description the MPC9894 is a quad differential redundant input clock generator . the device contains logic for clock failure detection and auto switching for clock redundant applications . the generator uses a fully integrated pll to generate clock signals from any o ne of four redundant clock sources. the pll multiplies the frequency of the input reference clock by one, two, four, eight or divides the reference clock by two or four. the frequency-multiplied clock sig nal drives four banks of two differential outputs. each bank allows an individual frequency-divider configur ation. all outputs are phase-aligned 2 to each other. due to the external pll feedback, the clock signals of all outputs are also phase-aligned 2 to the selected input reference clock, providing virtually zero-delay capability. the integrated idcs contin uously monitors all four clock inputs and indicates a clock failure for each clock input. when a fals e clock signal is detected on the active clo ck, the MPC9894 switches to a redundant clo ck input, forcing the pll to slowly slew t o align- ment and not produce any phase bumps at the outputs. the MPC9894 also provides a manual mode that allows for user-controlled clock switches. the device is packaged in a 11x11 mm 2 100-ball mapbga package. 1. final specification subject to change. 2. at coincident rising edges. MPC9894 quad input redundant idcs clock generator vf suffix 100-lead map bga package case 1462
MPC9894/d 2 timing solutions table of contents device description ............................................................................................................ ........... 4 operation information ......................................................................................................... ..... 7 basic functional description .................................................................................................. ... 7 definitions ................................................................................................................... ............. 7 device configuration .......................................................................................................... ....... 8 i 2 c configuration and i 2 c addressing ..................................................................................... 8 idcs mode configuration ...................................................................................................... 8 automatic idcs mode ........................................................................................................... .. 8 clock failure detection ....................................................................................................... .... 9 clearing of idcs alarm flags ................................................................................................. 9 idcs manual mode .............................................................................................................. .10 interrupt operation ........................................................................................................... ..... 10 clock operation on power-up ............................................................................................... 10 pll feedback .................................................................................................................. ..... 10 pll out-of-lock conditions .................................................................................................. 10 c lock output transition ........................................................................................................... 1 1 input and output frequency configuration .................................................................. 12 i 2 c interface and configuration/status registers .................................................... 13 ieee std.1149.1(jtag) .. ................ ................ ................ ................ ............. ............. ............. ............ 18 power supply configuration ................................................................................................ 19 MPC9894 programming model ................................................................................................. 27
MPC9894/d timing solutions 3 list of tables table 1: pin configurations .................................................................................................... ............... 4 table 2: function table ........................................................................................................ ................. 6 table 3: MPC9894 idcs configuration ............................................................................................ ..... 8 table 4: input clock qualifier and status flag ................................................................................. ..... 9 table 5: input clock status clk_stat[3:0] ...................................................................................... ... 9 table 6: clock input qualifier clk_valid[3:0] .................................................................................. ... 9 table 7: sel_stat[1:0] ......................................................................................................... ............... 9 table 8: configuration of pll p, m and n frequency dividers ........................................................... 12 table 9: input and output frequency ranges ..................................................................................... ... 12 table 10: i 2 c registers ................................................................................................................... ...... 13 table 11: slave address (register 0 ? read only) ............................................................................. 13 table 12: output configuration register (register 1 ? read/write) .................................................... 14 table 13: pll output divider n (fsel_a to fsel_d) ......................................................................... 14 table 14: mode configuration and alarm reset register (register 2 ? read/write) .......................... 14 table 15: individual reset of clk_stat[x] bits ................................................................................. .... 14 table 16: MPC9894 idcs configurationa .......................................................................................... ... 14 table 17: device configuration and output clock enable register (register 3 ? read/write) .......... 15 table 18: interrupt signal (int) enable int_e .................................................................................. .... 15 table 19: input clock qualifier enable qual_en ................................................................................ 1 5 table 20: slew control ......................................................................................................... ................. 15 table 21: output clock stop/enable ............................................................................................. ........ 15 table 22: input and feedback divider configuration register (register 4 ? read/write) .................. 16 table 23: input_fb_div[3:0] .................................................................................................... .............. 16 table 24: status register (register 5 ? read only) ............................................................................ 1 6 table 25: output power-up register (register 6 ? read/write) ......................................................... 17 table 26: clock output power-up bits ........................................................................................... ....... 17 table 27: feedback power-up register (register 7 ? read/write) .................................................... 17 table 28: feedback output power-up bit ......................................................................................... .... 17 table 29: tap interface signals ................................................................................................ ............ 18 table 30: instruction register ................................................................................................. ............... 18 table 31: tap controller public instructions ................................................................................... ...... 18 table 32: device idenitfication register ....................................................................................... ......... 18 table 33: power supply configuration ........................................................................................... ....... 19 table 34: absolute maximum rating s .............. ................. ................ ................ ................ ......... 20 table 35: general specifications .............................................................................................. 2 0 table 36: dc characteristics (tj = -40 c to +110 c) ................................................................. 20 table 37: pecl dc characteristics (tj = -40 c to +110 c) ...................................................... 21 table 38: lvcmos i/o dc characteristics (tj = -40 c to +110 c) ........................................... 21 table 39: ac characteristics (tj = -40 c to +110 c) ................................................................. 22 table 40: MPC9894 pin listing .................................................................................................. ........... 24 table 41: MPC9894 pin diagram .................................................................................................. .... 26 table 42: slave address (register 0 ? read only) ............................................................................. 27 table 43: output configuration register (register 1 ? read/write) .................................................... 27 table 44: mode configuration and alarm reset register (register 2 ? read/write) .......................... 27 table 45: device configuration and output clock enable register (register 3 ? read/write) .......... 27 table 46: input and feedback divider configuration register (register 4 ? read/write) .................. 27 table 47: status register (register 5 ? read only) ............................................................................ 2 7 table 48: output power-up register (register 6 ? read/write) ......................................................... 27 table 49: feedback power-up register (register 7 ? read/write) .................................................... 27
MPC9894/d 4 timing solutions device description table 1. pin configurations pin i/o type function supply active state clock inputs and outputs clk0, clk0 clk1, clk1 clk2, clk2 clk3, clk3 input lvpecl pll reference clock inputs (differential) (internal pulldown) vddic ? fb_in, fb_in input lvpecl pll feedback signal input (differ ential). when configured for external feedback, the qfb output should be connected to fb_in. (internal pulldown) vddic ? qa[1:0], qa[1:0] output lvpecl bank a differential outputs vddab ? qb[1:0], qb[1:0] output lvpecl bank b differential outputs vddab ? qc[1:0], qc[1:0] output lvpecl bank c differential outputs vddcd ? qd[1:0], qd[1:0] output lvpecl bank d differential outputs vddcd ? qfb, qfb output lvpecl differential pll feedback output. qfb must be connected to fb_in for correct operation vddcd ? control inputs and outputs ex_fb_sel input lvcmos selects between exte rnal feedback and internal feedback vdd high clk_valid[3:0]a input lvcmos validates the clock inputs clk0 to clk3 (internal pullup) vdd high figure 1. MPC9894 block diagram 3m/p p p 2, 4, 8, 16 2, 4, 8, 16 2, 4, 8, 16 2, 4, 8, 16 idcs pll 340 - 680 mhz fb comp fcomp 1 0 i 2 c interface control logic clk0 clk0 fb_in clk1 clk1 clk2 clk2 clk3 clk3 fb_in ex_fb_sel clk_valid[3:0] clk_alarm_rst pll_bypass scl sda addr[0:2] mboot media preset mr jtag[4:0] pll_tst[2:0] tpa mstrout_en qa0 qa0 qa1 qa1 qb0 qb0 qb1 qb1 qc0 qc0 qc1 qc1 qd0 qd0 qd1 qd1 qfb qfb clk_stat[3:0] sel_stat[1:0] 00 01 10 11 int busy lock
MPC9894/d timing solutions 5 a. bit order = msb to lsb. clk_alarm_rst input lvcmos reset of all four alarm stat us flags and clock selection status flag (internal pullup) vdd low pll_bypass input lvcmos select static test mode (internal pulldown) vdd high media input lvcmos output impedance control vdd high mr input lvcmos device reset (internal pullup) vdd low lock output lvcmos pll lock indicator vdd low clk_stat[3:0] output lvcmos clock input status indicator vdd high sel_stat[1:0] output lvcmos reference clock selection indicator vdd high busy output lvcmos idcs switching activity indicator vdd low mboot input lvcmos activates i 2 c boot sequence (internal pulldown) vdd high preset input lvcmos enables preset configuration of configuration regi sters on release of mr (internal pulldown) vdd high int output od indicate any status idcs change vdd low mstrout_en input lvcmos master enable for all outputs (internal pulldown) vdd high sel_2p5v input lvcmos device core power supply selection for vdd and vdda vdd high i 2 c interface scl i/o od i 2 c interface control, clock vdd ? sda i/o od i 2 c interface control, data vdd ? addr[2:0] input lvcmos i 2 c interface address lines (10k pullup) vdd high ieee 1149.1 and test tms input lvcmos jtag test mode select(10k pullup) vddic ? tdi input lvcmos jtag test data input(10k pullup) vddic ? tdo output lvcmos jtag test data output vddic ? tck input lvcmos jtag test clock vddic ? trst input lvcmos jtag test reset(10k pullup) vddic ? pll_test[2:0] input lvcmos pll_test pins (factory use only, must be connected to gnd) n/a ? tpa output lvcmos pll analog test pin (factory use only, must be connect to gnd) vdda ? power and ground gnd supply ground negative power supply ? ? vdd supply ? positive power supply for the device core, output status and control inputs. (3.3 v or 2.5 v) ?? vddab supply ? supply voltage for output banks a and b (qa0 through qb1) (3.3 v or 2.5 v) ?? vddcd supply ? supply voltage for output banks c and d (qc0 through qd1) and qfb (3.3 v or 2.5 v) ?? vddic supply ? supply voltage for differentia l inputs clock inputs clk0 to clk3 and fb_in (3.3 v or 2.5 v) ??- vdda supply ? clean supply for anal og portions of the pll (this voltage is derived via a rc filter from the v dd supply) ?? table 1. pin configurations (continued) pin i/o type function supply active state
MPC9894/d 6 timing solutions a. the combined pins of lock = 1 and busy = 0 are used to indicate a catastropic failure. refer to section ?pll out-of-lock conditions.? table 2. function table control default 0 1 control inputs pll_bypass 0 pll enabled. the input to output frequency relationship is according to table 9 if the pll is frequency locked. pll bypassed and idcs disabled. the vco output is replaced by the reference cl ock signal fref. this is considered to be a test mode and clock monitoring and clock switching are disa bled during this operation. clk_valid[3:0] 0 the associated clock i nput is considered to be invalid and usable the associated clock input is considered to be a valid usable clock input clk_alarm_rst 1 clk_stat[3:0] and sel_stat[1:0] flags are reset: clk_stat[3:0] = 0000 and sel_stat[1:0] = 00. clk_alarm_rst is an one-shot function. clk_stat[3:0] and sel_stat[1:0] flags are active mr 1 reset of data generators and output dividers. the MPC9894 requires reset at power-up and after any loss of pll lock. loss of pll lock may occur when the external feedback path is interrupted. the length of the reset pulse should be greater than two reference clock cycles outputs enabled (active) mboot 0 i 2 c read/write mode i 2 c boot mode preset 0 normal operation uses configur ation register preset values on mr ex_fb_sel 0 selects internal feedback path selects external feedback path media 0 low output impedance (qa0 to qd1 and qfb) 50 ? output impedance (qa0 to qd1 and qfb) sel_2p5v 0 selects 3.3 v for core v dd selects 2.5 v for core v dd mstrout_en all outputs disabled (synchronou s with clock being low) all outputs enabled control outputs lock a pll is locked pll is unlocked busy a the idcs has initiated a clock switch. no clock switch currently performed int idcs status has changed (indicates an assertion of clk_stat[3:0] or deassertion of lock ) no status change clk_stat[3:0] associated clock input not valid associated clock input valid sel_stat[1:0] encoded value refer to table 7 encoded value refer to table 7
MPC9894/d timing solutions 7 operation information basic functional description the MPC9894 is a quad-redundancy idcs clock genera- tor. the redundancy feature allo ws automatic switching from the reference clock source to a secondary clock source on de- tection of a failed reference clock. the MPC9894 will detect and report a missing clock on any of its four inputs. based upon the current idcs mode setting and the qualifier input pins, the MPC9894 will switch to the next qualified secondary clock. the input clock sources, cl k0, clk1, clk2, and clk3, are assumed to be the same frequency 1 but non-phase-related sources. when a clock switch occurs, the phase alignment to the new clock source will occur over an extended time period, eliminating runt clock output pulses. the maximum rate of phase change is specified in the ac parameter delta period per cycle( ? per/cyc). the device uses a fully integrated pll to generate clock signals from redundant clock sources. the pll multiplies the input reference clock signal by a variety of values, including 0.25, 0.5, 1, 2, 4 or 8. for a complete list refer to table 9. the frequency multiplied clock signal drives four independent output banks. each output bank is phase-aligned to the input reference clock phase, providing virtually zero-delay capability 2 . the configuration of the MPC9894 series of clock genera- tors is performed through either the i 2 c interface or by the pre- set configuration mode. the i 2 c interface uses a 2 pin interface to transmit clock and data to and from a series of configuration and status registers in the MPC9894. definitions idcs: intelligent dynamic clock swit ch. the idcs monitors the clock inputs clk0, clk1, clk2, and clk3. upon a failure of the reference clock signal, the idcs switches to a qualified sec- ondary clock signal and the status flags are set. reference clock signal: the input clock signal that is selected by the idcs or idcs_mode[2:0] as the i nput reference to the pll. primary clock: the input clock signal sele cted by idcs_mode[2:0]. the primary clock may or may not be the reference clock, depend- ing on idcs mode and idcs status. secondary clock: the input clock signal which will be selected by the idcs upon an automatic clock switch. tertiary, quaternary clocks: the input clock signals that will be selected by the idcs, in turn, after the current secondary clock. th is clock selection is based upon a round robin rotational sequence manual idcs mode: the reference clock input is selected by idcs_mode[0xx]. automatic idcs mode: the reference clock signal is determined by the idcs. selected clock: the sel_stat[1:0] flags indi cate the reference clock signal. qualified clock: the corresponding clk_valid[3:0] signal is logic high, the associated clk_stat status bit is logic high and no clock failure is present. bit ordering: the bit ordering convention used in this document for both pin and register documentation is name[7:0] where bit 7 is the most significant bit and 0 is the least significant bit. 1. refer to table 39 for cl ock frequency specification 2. using external feedback
MPC9894/d 8 timing solutions device configuration i 2 c configuration and i 2 c addressing the MPC9894 is configured via a series of 8-bit registers. the bits in these registers allow a wide range of control over the operation of the MPC9894 clock generator. these registers are accessed via an i 2 c interface through which a 7-bit address is sent from the i 2 c master to select the specific i 2 c slave device being accessed. the address for this clock driver is found in the first of the MPC9894 i2c register s. the format of this address has a fixed most-significant four bits of binary 1101 while the least-significant 3 address bits are read from the 3 addr pins. this provides the capability to configure up to 8 clock devices on a single i 2 c interface. in addition, activation of the mboot pin on power-up or re- set initiates a automatic boot sequence allowing the clock gen- erators to be initialized from a i 2 c compatible eeprom. in this case the MPC9894 becomes an i 2 c master and the configura- tion bits are filled by the information from the first 6 bytes of the eeprom. this allows the clock to be configured without a con- trolling i 2 c bus master if desired. the preset pin allows the device to be configured without a i 2 c bus master. the detailed register descripti ons are found in the section, i 2 c interface and configurat ion/status register. idcs mode configuration three register bits are used to configure the MPC9894 in either an automatic clock switch mode or into a manual clock select mode. the three mode select bits are defined in table 3. idcs modes 000 through 011 allow manual selection be- tween the four clock sources. idcs modes 100 through 111 en- able the automatic mode of the idcs. a. for clk_valid[3:0] = 1111 and input clock validity automatic idcs mode in the automatic mode, the cl ock failure detection is en- abled and the idcs overwrites the selected clock on a clock failure. the idcs operation requires pll_bypass = 0 and idcs_mode[2] = 1. the reference clock is handled in a round robin method based upon clock va lidity and the qualification in- put clk_valid[3:0]: the qualific ation input is obtained from the four input pins, clk_valid[3:0]. if any of the clk_valid pins are low the associated clock input will be considered ?un- qualified? and thus not selected as a reference clock. alterna- tively, if a clock input does not have a valid clock signal, it will not be selected and the next qualified and valid clock is selected as the reference clock. for example, if idcs_mode[2: 0] = 100 (the idcs is in au- tomatic mode), clk_valid[3:0] = 1111 and clk0, clk1, clk2, and clk3 have valid input clock signals then clk0 is the primary clock and clk1 is the secondary clock. the idcs se- lects the primary clock as the reference clock and the pll will phase-lock the clock outputs to the clk0 input. upon the failure of clk0 the idcs will select clk1 as the reference clock and initiate a switch, making clk1 the reference clock and clk2 the secondary clock. if clk1 fail s, the idcs will switch to clk2, etc. a de-asserted clk_valid[] pin disables the associated clock input as secondary clock. the associated clock input can- not be selected by the idcs as secondary clock signal. for in- stance, if clk0 is the primary clock and clk_valid[3:0] = 1101, the idcs will select clk2 upon a clock failure of clk0 (clk1 is disabled by the clk_valid1 in- put, allowing external logic to control the idcs switch logic). if a clock is the reference clock signal and its associated clk_valid signal is switched from ?valid' to ?invalid', the idcs initiates a clock input switch, selecting the next available clock input (secondary clock). an invalid clock 1 signal triggers the associated clock status output (clk_stat[3:0]), independ ent of the primary and refer- ence clock. these pins go set on a clock failure and remain set (sticky) until the clk_alarm_rst pin or the individual alarm re- set bits (alarm_rst[3:0]) are asserted. the clk_stat[3:0] outputs are mirrored in the device register 4 for i 2 c bus access. after each successful idcs-commanded switch, the pri- mary clock as set by idcs_mode[1xx] is no longer the refer- ence clock. the user may reset the idcs flags by asserting the individual alarm_rst[3:0] bits after each idcs-commanded switch. activation of alarm_rst[ 3:0] does not change the ref- erence clock. a user-commanded change of the primary clock in automatic mode requires a write command to the idcs_mode[2:0] = 0xx bits (the primary clock and sel_stat[1:0] can be freely changed by setting idcs_mode[2:0] = 1xx). if the refe rence clock is not the prima- ry clock, a write command to idcs_mode[2:0] = 1xx will cause the pll to lock on the primary clock, given the new primary clock is a qualified clock. table 3. MPC9894 idcs configuration idcs_mode [2:0] description primary clock secondary clock a tertiary clock quaternary clock 000 manual clk0 n/a n/a n/a 001 clk1 n/a n/a n/a 010 clk2 n/a n/a n/a 011 clk3 n/a n/a n/a 100 automatic clk0 clk1 clk2 clk3 101 clk1 clk2 clk3 clk0 110 clk2 clk3 clk0 clk1 111 clk3 clk0 clk1 clk2 1. see ?clock failure detection? on page 9 .
MPC9894/d timing solutions 9 a. the input qualifier logic can be enabled or dis abled by setting the qual_en bit in register 3. the sel_stat[1:0] pins indica te which of the four input clocks is the current reference cl ock. in the auto matic mode and in the case of the reference clock failure, the sel_stat flag will indicate a reference clock diffe rent from the original primary clock selected by idcs_mod e[2:0]. the clk_stat outputs are mirrored in register 5, bits 1:0 for i 2 c bus access. if all four clock inputs are not qualified the vco will slew to its lowest frequency. this condition will be indicated by the lock pin being de-asserted. the MPC9894 will remain in this state until an input clock is restored and the device is reset via the mr pin. clock failure detection the MPC9894 clock failure dectection is performed using an input clock amplitude check combined with an activity detec- tor. the following conditions wil l trigger a failed clock status (clk_statn = 0) on any qualified clock (clk_validn = 1). these conditions are: 1 . either or both clkx, clkx are disconnected from the input clock source and open. 2 . clkx and clkx are shorted together 3 . either or both clkx or clkx are shorted to gnd 4 . both clkx and clkx are shorted to a power supply 5 . amplitude of clkx or clkx is less than v pp, ok (refer to ac specification, table 39) in addition, the currently selected clock is checked by a phase-frequency detector after the in put divider (p). this is trig- gered by a phase step of mae( ? ). this phase detector will issue a failed clock status (clk_sta tn = 0) within 'p' clock cycles. the idcs does not detect c hanges of the reference fre- quency or the reference frequency being out of the specified in- put frequency range. this includes errors such as reference fre- quency drift due to crystal aging etc. clearing of idcs alarm flags the input clock status flags are set by a clock failure and remain set until manually clear ed (sticky). clearing can be done by either of two methods. all stat us flags can be cleared by the package pin, clk_alarm_rst . or individual status flags can be cleared via register bits, alarm_rst[3:0]. the clk_alarm_rst pin is activated by a negative edge on the pin. this clears all clk_stat[3:0] flags and returns the idcs to the primary clock source. the sel_s tat[1:0]-selected clock indi- cator now reflects the i dcs_mode[2:0] setting. by using alarm_rst[3:0] (register 2) individual clk_stat[3:0] bits are cleared by writing a logic 0 to the indi- vidual bit in this register. it is important to note that this action does not return the idcs to the primary clock. table 4. input clock qualifier and status flag input clock associated input qualifier a associated input clock status flag pin register location clk0 clk_valid0 clk_stat0 device register 5, bit 3 clk1 clk_valid1 clk_stat1 device register 5, bit 4 clk2 clk_valid2 clk_stat2 device register 5, bit 5 clk3 clk_valid3 clk_stat3 device register 5, bit 6 table 5. input clock status clk_stat[3:0] clk_stat[] description 0 clock input failure 1 clock input signal valid table 6. clock input qualifier clk_valid[3:0] clk_valid[] associated input clock 0 not qualified and will not be selected 1 qualified table 7. sel_stat[1:0] sel_stat[1:0] selected clock input 00 clk0 01 clk1 10 clk2 11 clk3
MPC9894/d 10 timing solutions idcs manual mode the manual request idcs mode is selected by idcs_mode[2:0] = 0xx. the pll functions normally and all four inputs clocks are monitored. the reference clock will al- ways be the clock signal selected by idcs_mode[1:0] and will be indicated by sel_stat[1:0]. a manual-requested clock switch (by changing the idcs_mode[0xx] signal) will only be executed if the new clock is va lid. the sel_stat[1:0] pins/bits should be checked after the manual request to ensure the clock switch occurred. interrupt operation the MPC9894 pin, int , may be used to interrupt a micro- processor or microcontroller. this open drain output pin goes active or low on any of the following occurrences 1 . a clock failure as indicated by any of bits 6 thru 3 being set in the status register 2 . a out-of-lock condition for the pll as indicated by either the lock pin or bit 2 of the status register. the interrupted processor would then use the i 2 c interface to read the status register (bit 7) to determine if this MPC9894 generated the interrupt. if t he interrupt was caused by this mc9894, the status register wo uld then be analyzed to deter- mine the reason for the interrupt and then the appropriate action taken. in order for interrupts to occur, the int_e bit must be set in the device configuration and output clock enable register. once the interrupt flag has been set, reading of the status reg- ister clears the int flag. clock operation on power-up on or after power-up, the MPC9894 must be reset via the mr pin. the MPC9894 may be powered-up in either of three configurations. these configurat ions are selected by the pre- set pin and mboot pin. if preset is low, on release of the mr pin, the MPC9894 powers up in a benign mode with all clock outputs disabled. the device is ready to be and must be programmed via the i 2 c in- terface prior to operation. if the preset pin is high on the release of the mr pin, the MPC9894 powers up in a run state. in this case the idcs is con- figured for automatic mode, clk0 to be the primary clock, a di- vide by 2 on clock bank a and b outputs, a divide by 8 on clock c and d outputs, all clock output banks enabled and interrupts enabled. if using the preset mode, then at least one of the clock inputs must have the correct input frequency prior to mr going high. later in this document, tables defining the i 2 c interface registers describe both configurations. the default (reset) infor- mation is for the normal reset operation, while the default (pre- set) information describes the values for each configuration bit on activation of the preset pin. in order to return the MPC9894 to either the preset or reset configuration the mr pin must be activated. refer to the boot mode section for a description of the mboot pin. pll feedback the MPC9894 may be operated with either an internal or an external pll feedback path. the selection of internal vs. ex- ternal feedback is made with the pin, ex_fb_sel. if external feedback is desired, the ex_fb_sel pin should be connected to vdd and a connection from qfb/ qfb to fb_in/ fb_in must be made. external feedback provides a known relationship be- tween the clock input and the feedback input for phase synchro- nization of output clock signals to the clock input. if this phase synchronization is not required, the MPC9894 may be config- ured for internal feedback by the connection of ex_fb_sel to ground. in this configuration, the connection from the feedback output to the feedback input is not required. the feedback out- put may be used as a separate output to produce a reference clock output. pll out-of-lock conditions the lock pin and associated status bit indicates the lock state of the pll. after power-up and prior to writing configura- tion data to the control registers, an out-of-lock condition will be indicated by lock = 1. if a valid clock is available and proper configuration data is written to the control registers, lock will then indicate the pll is in a locked condition with lock =0. the combination of lock = 1 and busy = 0 is used to in- dicate a catastrophic failure of the pll. this condition will occur on the following: 1. all input clocks have faile d or no clock is present. 2. external feedback has been selected with the ex_fb_sel pin and an external feedback signal is not present on the fb_in/ fb_in inputs. it should be not ed that if this condition occurs during the initial pll lock acquisition the pll will produce a clock that is locked to the internal feedback path. however, the catastrophic failure status of lock = 1 and busy = 0 will occur. recovery from the catastrophic failure condition requires repairing the cause of the failure, followed by a master reset to be issued to the MPC9894.
MPC9894/d timing solutions 11 clock output transition a MPC9894 clock switch, eit her in idcs manual or idcs automatic mode, follows the next positive ed ge of the newly se- lected reference clock signal. the positive edge of the feedback clock and the newly selected reference clock edge will start to slew to alignment by adjusting the feedback edge placement a small amount of time in each clock cycle. figure 2 ?clock switch? shows a failed primary input clock with the MPC9894 switching to and aligning to the secondary clock. this small amount of additional time in each clock cycle will ensure that the output clock does not have any large phase changes or fre- quency changes in a short period of time. the alignment will be to either 1) the closest edge, either forward or backward or 2) toward the lagging clock edge. the maximum rate of period change is specified in the ac parameter tables with the param- eter of ? per/cyc. this parameter imp lies that the output clock edge will never change more than the specified amount in any one cycle. the busy signal is used to indicate that the MPC9894 is in the process of slewing to the new input clock alignment. the signal is accessed thru the busy pin and goes set upon a clock switch. the pin is reset once the phase realignment is complet- ed. during the period that busy is active, the configuration reg- ister of the MPC9894 should not be written with new configura- tion data. for example, if the current i nput clock of 62.5 mhz and the secondary clock are 180 degrees out of phase then the mini- mum clock transiition time can be calculated by t cycle =1 f cycle =1 62.5 mhz = 16 ns therefore 180 degree clock difference is t cycle 2 = 8 ns assuming a ? per/cyc of 40 ps, then 8ns 40 ps/cycle = 200 cycles. this is the minimum number of cycles that will be required for the alignment to the new clock. the alignment to the new clock phase may occur slower than this but never faster. the alignment on clock failure is selectable between either 1) the closest edge, either forwar d or backward or 2) toward the lagging clock edge. the select ion of the alignment method is selected in the slew_control bit (bit 5) of the device configura- tion and output enable register. this selection allows the user to select the alignment method that best suits the application. the characteristics and subsquent advantages and disadvan- tages of each method are described as follows. 1 . slew to closest edge a. the alignment is either forward toward the lagging edge or backward toward the leading edge. b. the alignment to the closest edge ensures re-align- ment to the new clock input in the minimum time. c. in applications where the input clocks are closely aligned, there is no ambiguity on the direction of clock slew. d. the clock output frequency wi ll either increase or de- crease based on direction of clock slew. 2. slew to lagging edge a. the output frequency alwa ys decreases. thus the clock frequency never viol ates a maximum frequency specification in the user system. b. when input clocks are closel y aligned (within spo + jit- ter) the MPC9894 may align to the closest edge or to the lagging edge. in the case of multiple MPC9894s with equivelent clock inputs one MPC9894 may align in one direction while an other MPC9894 may align to the opposite direction. if default values for the slew_control is not the configura- tion desired then the reconfigurat ion of the slew method should be perform soon after power-up and the configuration should remain fixed from that point. busy output clock secondary clock primary clock busy figure 2. clock switch
MPC9894/d 12 timing solutions input and output frequency configuration configuring the MPC9894 input and output frequencies re- quires programming the internal pll input, feedback and out- put dividers. the output frequency is represented by the follow- ing formula: f out =[(f ref p) ? m] n where f ref is the reference frequency of the selected input clock source (reference input), m is the pll feedback divider and n is a output divider. the pll input divider p, the feedback divider m and the output divider are configured by the device registers 1 and 4. the MPC9894 has four output banks (bank a, b, c, and d) and each output bank can be configured individ- ually as shown in table table 8. the reference frequency f ref and the selection of the pll input divider (p) and feedback-divider (m) is limited by the spec- ified vco frequency range. f ref , p and m must be configured to match the vco frequency range of 340 to 680 mhz in order to achieve stable pll operation: f vco,min (f ref p ? m) f vco,max the pll input divider (p) can be used to situate the vco in the specified frequency range. the pll input divider effec- tively extends the usable input frequency range. the output frequency for each bank can be derived from the vco frequency and output divider (n): f qa [1:0] = f vco n a f qb [1:0] = f vco n b f qc [1:0] = f vco n c f qd [1:0] = f vco n d table 9 illustrates the possible input clock frequency con- figurations of the MPC9894. note that the vco lock range is al- ways 340 mhz to 680 mhz, setting lower and upper boundaries for the frequency range of the device. figure 3. pll frequency calculation m n f ref f out p pll table 8. configuration of pll p, m and n frequency dividers divider available values configuration through pll input divider (p) 1, 32, 3, 4, 5, 6 input_fb_div[3:0], register 4, bit 3:0 pll feedback divider (m) 8, 12, 16 pll output divider, bank a (n a ) 2, 4, 8, 16 fsel_b[1:0], register 1, bit 7:6 pll output divider, bank b (n b ) 2, 4, 8, 16 fsel_b[1:0], register 1, bit 5:4 pll output divider, bank c (n c ) 2, 4, 8, 16 fsel_c[1:0], register 1, bit 3:2 pll output divider, bank d (n d ) 2, 4, 8, 16 fsel_d[1:0], register 1, bit 1:0 table 9. input and output frequency ranges input_fb_div[3:0] p m f ref range mhz output frequency for any bank a, b, c or d (fsel_x) and ratio to fref n=2 n=4 n=8 n=16 0 1 16 21.25 - 42.5 8 ? f ref 4 ? f ref 2 ? f ref f ref 1 1 12 28.33 -56.67 6 ? f ref f3 ? f ref 1.5 ? f ref 0.75 ? f ref 2 2 12 56.66 -113.34 3 ? f ref f1.5 ? f ref 0.75 ? f ref 0.375 ? f ref 3 1 8 42.5 - 85.0 4 ? f ref f2 ? f ref 1 ? f ref 0.5 ? f ref 4 2 16 42.5 - 85.0 4 ? f ref 2 ? f ref 1 ? f ref 0.5 ? f ref 5 reserved 6 2 8 85.0 - 170.0 2 ? f ref 1 ? f ref 0.5 ? f ref 0.125 ? f ref 7 3 12 85.0 - 170.0 2 ? f ref 1 ? f ref 0.5 ? f ref 0.125 ? f ref 8 4 16 85.0 - 170.0 2 ? f ref 1 ? f ref 0.5 ? f ref 0.125 ? f ref 9 reserved 10 4 12 113.32 - 226.64 1.5 ? f ref 0.75 ? f ref 0.375 ? f ref 0.1875 ? f ref 11 reserved 12 reserved 13 reserved 14 4 8 170.0 - 340.0 1 ? f ref 0.5 ? f ref 0.25 ? f ref 0.125 ? f ref 15 6 12 170.0 - 340.0 1 ? f ref 0.5 ? f ref 0.25 ? f ref 0.125 ? f ref
MPC9894/d timing solutions 13 i 2 c interface and configurat ion/status registers the following tables summarize the bit configurations for the registers accessible via the i 2 c interface. the register val- ues are read or written over the i 2 c interface by the i 2 c master. this sequence starts with the i 2 c start command, followed by the i 2 c device address and read/write byte. this is then fol- lowed by the address of the regist er that is to be accessed. in the case of a write, t he register address byte is followed by the data to be written to that register . in the case of a read, the de- vice will then respond with the data from that register. at the conclusion of the transfer an i 2 cstop command is issued by the master to terminate the transfer. for a complete description of the i 2 cprotocol refer to the v2.1 i 2 c specification. table 10 lists the registers t hat are accessible via the i 2 c interface. boot mode when the i 2 c boot mode is activated on power-up or reset via the mboot pin, the entire set of writable configuration reg- isters are written with a 6-byte sequence. this sequence starts with the output config uration register, and is followed by the mode configuration and alarm reset register, the device con- figuration and output clock enable register, the input and feedback divider configuration register, the output power-up register and the feedback power-up register. this equates to the register sequence of 1, 2, 3, 4, 6, 7. this sequence starts with the start command, the devic e select and read/write(write) byte, followed by the beginning byte address for reading from the eeprom. this is then follow ed by the start command, de- vice select and read/write (read) and four current address read bytes. the device address is the binary 7-bit value of 1010000. this i 2 c sequence is compatible with industry standard i 2 c bus eeproms such as stmicroelectr onics m24c01, or equivalent. slave address register the slave address register contains the i 2 c address that is used to determine if the data on the i 2 c interface is ad- dressed to this device. the seven-bit address is determined with the fixed value of binary 1101 followed by variable bits that are obtained from the three address pins. the three input pins allow for 8 different addresses for a given clock generator, al- lowing up to 8 clock generators to be addressed on a single i 2 c interface. table 10. i 2 c registers address register 0x00 table 11 ?slave address (register 0 ? read only)? 0x01 table 12 ?output configuration r egister (register 1 ? read/write)? 0x02 table 14 ?mode configuration and alarm re set register (register 2 ? read/write)? 0x03 table 17 ?device configuration and output cl ock enable register (register 3 ? read/write)? 0x04 table 22 ?input and feedback divider configur ation register (register 4 ? read/write)? 0x05 table 24 ?status register (register 5 ? read only)? 0x06 table 25 ?output power-up regi ster (register 6 ? read/write)? 0x07 table 27 ?feedback power-up regi ster (register 7 ? read/write)? start write start read stop ack ack ack noack dev selection dev selection data out byte addr figure 4. boot mode random access read table 11. slave address (register 0 ? read only) bit76543210 description not used addr_6 add_r5 addr_4 addr_3 addr_2 read from addr[2] pin addr_1 read from adr[1] pin addr_0 read from addr[0] pin reset default 1101 preset default 1101
MPC9894/d 14 timing solutions output configuration register the output configuration regi ster is divided into four, 2 bit-groups with each group selecting the divide ratio for output banks a through bank d, refer to table 12. for each bank, four output divider settings ( 2, 4, 8, 16) are available, refer to table 12. mode configuration register the mode configuration regist er, refer to table 14, is a read/write register and contains the fields for mode selection as well as alarm reset. the mode of the MPC9894 may be changed by writing the three least significant mode conf iguration register bits to the desired value. the current idcs mode of the MPC9894 may be obtained by reading this register. the alarm reset bits, found in bit positions 6 thru 3, may be used to individually reset the stat us flags of register 5. each of these flag bits are associated with the four clock inputs pins and indicate a failed clock input. clearing of a clock status flag is performed by writing a logic 1 to the individual bit (or bits if more than one flag is to be cleared). care should be taken to insure that the idcs mode information is written to the proper value when resetting the clock status bi ts. the four alarm reset bits al- ways read as a logic 0. if a clock input status flag is cleared and the clock input is still in a fail ed state, the status flag will go set within 4 clock cycles a fter being cleared. a. this is a repeat of table 3. b. for clk_valid[3:0] = 1111 and input clock validity. table 12. output configuration register (register 1 ? read/write) bit76543210 description fsel_a[1:0] fsel_b[1:0] fsel_c[1:0] fsel_d[1:0] reset default 0 0 0 0 0 0 0 0 preset default 0 0 0 0 1 0 1 0 table 13. pll output divider n (fsel_a to fsel_d) fsel_x[1:0] value 00 2 01 4 10 8 11 16 table 14. mode configuration and alarm reset register (register 2 ? read/write) bit76543210 description not used alarm_rst[3:0] (refer to table 15) idcs_mode[2:0] (refer to table 16) reset default n/a n/a n/a n/a n/a 0 1 1 preset default n/a n/a n/a n/a n/a 1 0 0 table 15. individual reset of clk_stat[x] bits alarm_rst[x] description 0 no action 1 the status flag clk_stat[x] is cleared by setting of this bit. (bit always reads as zero) table 16. MPC9894 idcs configuration a idcs_mode [2:0] description primary clock secondary clock b tertiary clock b quaternary clock b 000 manual clk0 n/a n/a n/a 001 clk1 n/a n/a n/a 010 clk2 n/a n/a n/a 011 clk3 n/a n/a n/a 100 automatic clk0 clk1 clk2 clk3 101 clk1 clk2 clk3 clk0 110 clk2 clk3 clk0 clk1 111 clk3 clk0 clk1 clk2
MPC9894/d timing solutions 15 device configuration and output enable register the device configuration and output enable register is used to individually enable or disable each bank of outputs. output banks are enabled by setting the corresponding bit to a logic 1 and disabled by setting the bit to a logic 0 as described in table 21 ?output clock stop/enable?. the disable logic sets the outputs of the addressed bank synchronously to logic low state (qx[] = 0 and qx[] = 1). t he clock output enable/stop bits can be set asynchronous to any clock signal without the risk of generating of runt pulses. th e pll feedback output qfb can- not be disabled when MPC9894 is configured for external feed- back. the device configuration register, bit 6, qual_en is used to enable or disable all clock input qualifier pins. asserting this bit enables the clock qualifier input pins clk_valid[3:0]. deasserting this bit disables these pins such that inputs on clk_valid[3:0] are ignored. the int_e bit, in bit position7, is used to enable or disable interrupts from occurring on the int pin. the setting of the inter- rupt flag (bit 7 of the status regi ster) is unaffected by this bit. table 17. device configuration and output clock enable register (register 3 ? read/write) bit76543210 description int_e qual_en slew_control enabl e_qfb enable_qa enable_qb enable_qc enable_qd reset default 0 0 0 0 0 0 0 0 preset default 1 1 0 0 1 1 1 1 table 18. interrupt signal (int ) enable int_e int_e description 0 interrupt signal int is disabled 1 interrupt signal int is enabled table 19. input clock qualifier enable qual_en qual_en description 0 clk_valid[3:0] are disabled (clo ck qualifier signal s are disabled) 1 clk_valid[3:0] are enabled (c locks can be qualified) table 20. slew control slew_control description 0 clock slew direction on clock switch is toward the closest edge 1 clock slew direction on clock switch is toward the lagging edge table 21. output clock stop/enable enable_qx description 0 output bank x is disabled (clo ck stop in logic low state) 1 output bank x is enabled
MPC9894/d 16 timing solutions input and feedback divide r configuration register the input and feedback divider configuration register is used to select the input divider value and the feedback divider values. the four bits for input _fb_div allow 16 combinations of input and feedback divider ratios. some input and output fre- quency ranges may overlap allowing a choice of pll closed loop bandwidths. this selection may be useful when pll devic- es are cascaded. device status register the device status register co ntains a copy of the status sel_stat[1:0], lock and clk_stat[3:0] pins. in addition, bit 7 is an int flag bit, which is used to indicate a setting of a bit in the clk_stat[3:0], a clearing of the lock bit and a change in the value of the sel_stat[1:0] bits. the clk_stat[3:0] bits are sticky and remain set until manually reset through the mode configuration register. the setting of the register int bit is reflected on the inter- rupt pin only if interrupts ar e enabled. enabling interrupts is done by the setting of the int_e bit which is located in the de- vice configuration register. reading of the status register clears the int flag. table 22. input and feedback divider configuration register (register 4 ? read/write) bit76543210 description reserved reserved res erved reserved input_fb_div[3:0] reset default n/a n/a n/a n/a 0 0 0 0 preset default n/a n/a n/a n/a 0 0 1 1 table 23. input_fb_div[3:0] input_fb_div[3:0] input divider (p) feedback divider (m) 0000 1 16 0001 1 12 0010 2 12 0011 1 8 0100 2 16 0101 reserved 0110 2 8 0111 3 12 1000 4 16 1001 reserved 1010 4 12 1011 reserved 1100 reserved 1101 reserved 1110 4 8 1111 6 12 table 24. status register (register 5 ? read only) bit76543 2 1 0 description int inverse of int signal clk_stat[3:0] status of clk3, clk2, clk1 and clk0 (sticky) copy of clk_stat[3:0] signal lock inverse of lock signal sel_stat[1:0] copy of sel_stat[1:0] signal
MPC9894/d timing solutions 17 output power-up register the output power-up register configures each of the 8 lvpecl outputs for either po wer-up or a power-down state. the use of these bits allows power consumption to be reduced when all of the clock outputs ar e not used. placing an output in the power-down condition is not synchronous with the clock edges. feedback power-up register the feedback power-up register bit 0 is used to configure the MPC9894 feedback output in either a power-up state or a power-down state. note this register bit is valid for internal feedback configuration only. when external feedback is select- ed qfb is always enabled and in a power-up state. the remain- ing bits of this register are unused and read as a logic 0. table 25. output power-up register (register 6 ? read/write) bit 76543 2 10 description pwr_qd1 pwr_qd0 pwr_qc1 pw r_qc0 pwr_qb1 pwr_qb01 pwr_qa1 pwr_qa0 reset default00000 0 00 preset default11111 1 11 table 26. clock output power-up bits pwr_qxx description 0 output power-down 1 output power-up table 27. feedback power-up register (register 7 ? read/write) bit 7 654321 0 description pwr_qfb reset default 0 preset default 1 table 28. feedback output power-up bit pwr_qfb description 0 feedback output power-down 1 feedback output power-up
MPC9894/d 18 timing solutions ieee std.1149.1(jtag) this section describes th e ieee std. 1149.1 compliant test access port (tap) and boundary scan architecture imple- mentation in the MPC9894. specia l private instructions are pro- vided to assist in production test control. these instructions combined with control of the te st mode inputs and the use of shared inputs and outputs provide for full production test mode access and control. test access port interface signals table 29 lists the tap interface signals and their descrip- tions. instruction register instructions table 31 lists the public instructions provided in the imple- mentation and their instruction co des. public instructions are accessible by the customer for board test and may also be used for production chip test. boundary-scan register a full description of the boundary scan register may be found in the bsdl file. device identification register (0x0281d01d) table 29. tap interface signals signal name description function direction active state tck test clock test logic clock. input - tms test mode select tap mode control input. input - tdi test data in serial test instruction/data input. input - trst_b test reset bar asynchronous test controller reset. input - tdo test data out serial test instruction/data output. output - table 30. instruction register bit position 43210 field ir capture-ir value 00001 table 31. tap controller public instructions instruction code enabled serial test data path bypass 11111 bypass register clamp 01100 bypass register extest 00000 boundary scan register highz 01001 bypass register idcode 00001 id register sample 00010 boundary scan register table 32. device idenitfication register bit position 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 field version part number manufacturer id value 00000010100000011101000000011101
MPC9894/d timing solutions 19 power supply configuration the MPC9894 operates from eit her a 3.3 v or 2.5 v voltage supply for the device core. the pin sel_2p5v is used to logi- cally indicate the core supply vo ltage. this selection is done by setting the pin to a logic 1 for 2.5 v or logic 0 for 3.3 v operation. the input and output supply voltage may be set for either 3.3 v or 2.5 v and can be individually set for inputs and banks of outputs. table 33 ?p ower supply configuration? lists the sup- ply pins and what pin or group of pins are associated with each supply. note, that for output skew and spo specifications to be valid the input, feedback input and output, and the output bank must all be at the sa me voltage level. a. vddic (supply of fb_in) must be equal to vddcd (suppl y of qfb) to ensure the spo specification is met. power supply se quencing and mr operation figure 5 defines the release time and the minumum pulse length for mr pin. the mr release time is based upon the pow- er supply being stable and within v dd specifications. refer to table 39 for actual parameter values. the MPC9894 may be configured after release of rese t and the outputs will be stable for use after lock indication is obtained. v dd must ramp up prior to or concurrent with the other power supply pins. it is reco mmended that the maximum slew rate for the v dd supply not exceed 0.5 v/ms. power supply bypassing the MPC9894 is a mixed analog/digital product. the differ- ential architecture of the mp c9894 supports low noise signal operation at high frequencies. in order to maintain its superior signal quality, all v cc pins should be bypassed by high-frequen- cy ceramic capacitors connected to gnd. if the spectral fre- quencies of the internally gener ated switching noise on the sup- ply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth clock outputs the MPC9894 clock outputs are differential lvpecl volt- age compatible. the outputs are designed to drive a single 50 ? impedance load that is pro perly terminated. the media pin is used to select between either of two output termination techniques. selection of media = 0 sets all of the outputs to drive up to 50 ohm parallel terminated (to vtt) transmission lines. with media = 1 the outputs are designed to drive 50 ? transmission line terminated with a single 100 differential load resistor. see figures 7 and 8 for diagrams of each of these termination tech- niques. note, that the traditional output pulldown resistors for emitter follower biasing are not required for the MPC9894. if external feedback is used, the qfb output must be terminated with the same technique as sele cted with the media pin. once a termination technique is chosen, that technique must be used for all MPC9894 outputs to guarantee output skew timing. the recommended termination technique is media = 1. this provides a simpler termination method and also reduces overall power consumption of the MPC9894. unused outputs may be powered-down via the output power-up and feedback power-up registers to conserve power. if external feedback is selected the programming of the pwr_qfb bit is ignored. table 33. power supply configuration supply voltage description value v dd positive power supply for the device core, output status and control inputs. (3.3 v or 2.5 v) 3.3 v or 2.5 v v ddab supply voltage for output banks a and b (qa0 through qb1) 3.3 v or 2.5 v v ddcd supply voltage for output banks a and b (qc0 through qd1) and qfb 3.3 v or 2.5 v v ddic a supply voltage for differential inputs clock i nputs clk0 to clk3 and fb_in 3.3 v or 2.5 v v dda clean supply for analog portions of the pll (this voltage is derived via an rc filter from the v dd supply) derived from v dd figure 5. mr operation mr v dd t reset_rel t reset_pulse figure 6. v cc power supply bypass v dd v dda MPC9894 tbd tbd tbd r s v dd
MPC9894/d 20 timing solutions a. absolute maximum continuous ratings are t hose maximum values beyond which damage to th e device may occur. exposure to these c onditions or conditions beyond those indicated may adversely affect device reliability. func tional operation at absolute-maximum-rated co nditions is not implied. b. v ddx references power suppl y pin associated with specific input pin. c. v ddx references power supply pin asso ciated with specific output pin. a. operating junction temperature impacts dev ice life time. maximum continuous operati ng junction temperature should be selected according to the application life time requirements (ref er to application note an1545 for more information). the device ac and dc parameters are specified up to 110 c junction temperature allowing the MPC9894 to be used in appl ications requiring indus trial temperature range. it is recommende d that users of the MPC9894 employ thermal m odeling analysis to assist in applying the j unction temperature specifications to the ir particular application. a. dc characteristics are design targets and pending characterization. b. i ddab, cd includes current through the output resistors (all outputs terminated to v tt ). c. i ddab, cd includes current through the output resistors (all outputs terminated to v tt ). table 34. absolute maximum ratings a symbol characteristics min max unit condition v dd supply voltage (core) -0.3 4.0 v v ddab, cd supply voltage (differential outputs) -0.3 4.0 v v ddic supply voltage (differential inputs) -0.3 4.0 v v dda supply voltage (analog supply voltage) -0.3 v dd v v in dc input voltage b -0.3 v ddx +0.3 v v out dc output voltage c -0.3 v ddx +0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature -65 125 c table 35. general specifications symbol characteristics min typ max unit condition v tt output termination voltage (lvpecl) v dd - 2 v lvpecl outputs mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v cdm esd protection (charged device model) 500 v lu latch-up immunity 200 ma c in input capacitance tbd pf inputs jc thermal resistance (j unction-to-ambient, junction-to-board, junction-to-case) tbd c/w t j junction temperature a -40 110 c table 36. dc characteristics (t j =-40 c to +110 c) a symbol characteristics min typ max unit condition supply current for v dd = 2.5 v5% and v ddab,cd = 2.5 v5% i dd maximum quiescent supply current (core) tbd tbd ma v dd pins i ddab, cd b maximum quiescent supply current, outputs terminated 50 ? to v tt tbd tbd ma v ddab and v ddcd pins i dda maximum supply current (analog supply) tbd tbd ma v dda pin i ddic maximum quiescent supply current (i/o) tbd tbd ma v ddic pins supply current for v dd = 3.3 v5% and v ddab,cd = 3.3 v5% or v ddab,cd = 2.5 v5% i dd maximum quiescent supply current (core) tbd tbd ma v dd pins i ddab, cd c maximum quiescent supply current, outputs terminated 50 ? to v tt tbd tbd ma v ddab and v ddcd pins i dda maximum supply current (analog supply) tbd tbd ma v ddin pins i ddic maximum quiescent supply current (i/o) tbd tbd ma v ddic pins
MPC9894/d timing solutions 21 a. dc characteristics are design targets and pending characterization. b. clock inputs driven by pecl compatible signals. c. v pkpk is the minimum differential input voltage swi ng required to maintain ac characteristics. d. v cmr (dc) is the crosspoint of t he differential input signal. functi onal operation is obtained when t he crosspoint is within the v cmr (dc) range and the input swing lies within the v pp (dc) specification. a. dc characteristics are design targets and pending characterization. b. inputs have pull-down resistors affecting the input current. table 37. pecl dc characteristics (t j =-40 c to +110 c) a symbol characteristics min typ max unit condition differential pecl clock inputs (clkx, clkx and fb_in, fb_in )b for v ddic = 3.3 v 5% or v ddic =2.5 v 5% v pkpk ac differential input voltage c 0.2 1.3 v differential operation v cmr differential cross point voltage d 1.25 v dd -0.3 v differential operation i in input current a 100 ma v pp = 0.8 v and v cmr =v ddl -0.7 v differential pecl clock outputs (qa0 to qd1 and qfb) for v ddab,cd = 3.3 v 5% or v ddab,cd = 2.5 v 5% v oh output high voltage tbd v ddab,cd -1.0 tbd v termination 50 ? to v tt v ol output low voltage tbd v ddab,cd -1.7 tbd v termination 50 ? to v tt z out output impedance media = 0 media = 1 tbd 50 ? ? see figure 7 see figure 8 table 38. lvcmos i/o dc characteristics (t j =-40 c to +110 c) a symbol characteristics min typ max unit condition single-ended lvcmos inputs for v dd = 3.3 v 5% v ih input high voltage 2.0 v dd + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos v oh output high voltage 2.4 v i oh =-6 ma v ol output low voltage 0.4 v i ol =6 ma z out output impedance 40 62 ? i in input currentb 10 av in =v ddl or gnd single-ended lvcmos inputs for v dd = 2.5 v5% v ih input high voltage 1.7 v dd + 0.3 v lvcmos v il input low voltage 0.7 v lvcmos v oh output high voltage 1.9 v i oh =-6 ma v ol output low voltage 0.4 v i ol =6 ma z out output impedance 45 70 ? i in input currentb 10 av in =v ddl or gnd
MPC9894/d 22 timing solutions table 39. ac characteristics (t j =-40 c to +110 c) a b symbol characteristics min typ max unit condition v dd = 3.3 v 5%, v ddab,cd,ic = 3.3 v 5% or v ddab,cd,ic = 2.5 v 5% input and output timing specification f ref input reference frequency input reference frequency in pll bypass modec 21.25 28.33 56.66 42.5 85.0 113.32 170 42.5 56.67 113.34 85 170 226.68 340 tbd mhz mhz mhz mhz mhz mhz mhz mhz input_fb_div[3:0] = 0 input_fb_div[3:0] = 1 input_fb_div[3:0] = 2 input_fb_div[3:0] = 3,4 input_fb_div[3:0] = 6,7,8 input_fb_div[3:0] = 10 input_fb_div[3:0] = 14,15 pll bypass f vco vco frequency ranged 340 680 mhz f max output frequency 2 output 4 output 8 output 16 output 170.0 85.0 42.5 21.25 340.0 170.0 85.0 42.5 mhz mhz mhz mhz pll locked f refdc reference input duty cycle 40 60 % f refacc input frequency accuracye 500 ppm mae ( ? ) misaligned edge specification 600 1600 ps t r , t f output rise/fall time 800 ps 20% to 80% dc output duty cycle 47.5 50 52.5 % f i2c i 2 c frequency range 100 khz differential input and output voltages v pp differential input voltagef (peak-to-peak) (pecl) 1.3 v v pp, ok differential input voltageg (peak-to-peak) (pecl) tbd v v pp, nok differential input voltageh (peak-to-peak) (pecl) tbd v v o(p-p) differential output voltage ( peak-to-peak) (pecl) tbd 0.8 v pll and idcs specifications t ( ? ) propagation delay (static phase offset) clkx, clkx to fb_in, fb_in -100 +100 ps pll locked with external feedback selected t sk(o) output-to-output skew within a banki output-to-output skew across a banki 50 tbd ps ? per/cyc rate of change of periodj 2 output 4 output 8 output 16 output +40 +80 +120 +160 ps slew_control = 1 ? per/cyc rate of change of periodk 2 output 4 output 8 output 16 output 40 80 120 160 ps slew_control = 0 jitter and bandwidth specifications t jit(cc) cycle-to-cycle jitter rms (1 )10ps t jit(per) period jitter rms (1 )tbdps t jit(y) i/o phase jitter rms (1 )tbdps bw pll closed loop bandwidthl tbd khz
MPC9894/d timing solutions 23 a. ac characteristics are design targets and pending characterization. b. ac characteristics apply for par allel output termination of 50 ? to v tt . c. in bypass mode, the MPC9894 divides the input reference clock. d. the input reference frequency must match the vco lock range divided by the total feedback divider ratio: f ref =(f vco m) ? n. e. all input clock frequencies must be within this value to guarantee smooth phase transition on input clock switch. f. v pp is the minimum differential input voltage swing required to ma intain ac characteristics incl uding tpd and device-to-device ske w. g. v pp , ok is the minimum differential input voltage sw ing required for a vali d clock signal. above v pp, ok the input will be detected as a good clock (see idcs). h. v pp , nok is the maximum differential input voltage swing for a guaranteed bad clock. below v pp, nok the input will be detec ted as a failed clock (see idcs). i. v ddab =v ddcd . j. rate of period change is the maximum change of the clock output signal period t per cycle on a idcs commanded switch. k. rate of period change is the maximum change of the clock output signal period t per cycle on a idcs commanded switch. l. -3 db point of pll transfer characteristics. v dd = 3.3 v 5%, v ddab,cd,ic = 3.3 v 5% or v ddab,cd,ic = 2.5 v 5% mr and pll lock t lock maximum pll lock time 10 s t reset_ref mr hold time on power up 2 ps t reset_pulse mr hold time 100 ns table 39. ac characteristics (t j =-40 c to +110 c) a b (continued) symbol characteristics min typ max unit condition z = 50 rt = 50 ? v tt dut MPC9894 z=50 ? differential pulse generator z=50 ? rt = 50 ? v tt figure 7. MPC9894 ac test reference (media = 0) figure 8. MPC9894 ac test reference (media = 1) z = 50 ? rt = 100 ? dut MPC9894 z=50 ? differential pulse generator z = 50 ? rt = 50 ? v tt
MPC9894/d 24 timing solutions MPC9894 pin and package table 40. MPC9894 pin listing signal name description direction type active state supply pin clk0 clock0 positive input input lvpecl - vddic d1 clk0 clock0 negative input input lvpecl - vddic d2 clk1 clock1 positive input input lvpecl - vddic e3 clk1 clock1 negative input input lvpecl - vddic e2 clk2 clock2 positive input input lvpecl - vddic f3 clk2 clock2 negative input input lvpecl - vddic f2 clk3 clock3 positive input input lvpecl - vddic g1 clk3 clock3 negative input input lvpecl - vddic g2 fb_in feedback clock positive input input lvpecl - vddic c1 fb_in feedback clock negative input input lvpecl - vddic c2 qa0 positive differential clock output output lvpecl - vddab k4 qa0 negative differential clock output output lvpecl - vddab j4 qa1 positive differential clock output output lvpecl - vddab k5 qa1 negative differential clock output output lvpecl - vddab j5 qb0 positive differential clock output output lvpecl - vddab k7 qb0 negative differential clock output output lvpecl - vddab j7 qb1 positive differential clock output output lvpecl - vddab k6 qb1 negative differential clock output output lvpecl - vddab j6 qc0 positive differential clock output output lvpecl - vddcd a7 qc0 negative differential clock output output lvpecl - vddcd b7 qc1 positive differential clock output output lvpecl - vddcd a6 qc1 negative differential clock output output lvpecl - vddcd b6 qd0 positive differential clock output output lvpecl - vddcd a4 qd0 negative differential clock output output lvpecl - vddcd b4 qd1 positive differential clock output output lvpecl - vddcd a5 qd1 negative differential clock output output lvpecl - vddcd b5 qfb postive differential clock output output lvpecl - vddcd a3 qfb negative differential clock output output lvpecl - vddcd b3 clk_valid3 qualifier for clock input clk3 input lvcmos high vdd f10 clk_valid2 qualifier for clock input clk2 input lvcmos high vdd e10 clk_valid1 qualifier for clock input clk1 input lvcmos high vdd e9 clk_valid0 qualifier for clock input clk0 input lvcmos high vdd e8 clk_alarm_rst reset of all four alarm status flags and clock selection status flag input lvcmos low vdd f8 pll_bypass select pll of static test mode input lvcmos high vdd f9 media output impedance control (high = 50 ? ) input lvcmos high vdd e7 scl i 2 c interface control, clock i/o lvcmos - vdd c9
MPC9894/d timing solutions 25 sda i 2 c interface control, data i/o lvcmos - vdd c10 addr2 i 2 c interface control, address 2 (msb) input lvcmos - vdd a9 addr1 i 2 c interface control, address 1 input lvcmos - vdd b8 addr0 i 2 c interface control, address 1 (lsb) input lvcmos - vdd a8 mr device master reset input lvcmos low vdd d10 lock pll lock indicator output lvcmos low vdd g10 clk_stat3 input clk3 status indicator output lvcmos high vdd h9 clk_stat2 input clk2 status indicator output lvcmos high vdd h10 clk_stat1 input clk1 status indicator output lvcmos high vdd g8 clk_stat0 input clk0 status indicator output lvcmos high vdd g9 sel_stat1 reference clock selection i ndicator (msb) output lvcmos high vdd k8 sel_stat0 reference clock selection i ndicator (lsb) output lvcmos high vdd j8 busy idcs switch activity indicator output lvcmos high vdd j10 mboot activates i 2 c boot sequence input lvcmos high vdd d8 int indicates any status idcs change output od n/a vdd d9 preset sets preset state input lvcmos high vdd h7 tms jtag test mode select input lvcmos high vddic d3 tdi jtag test data input input lvcmos - vddic h1 trst jtag test reset bar input lvcmos low vdd h2 tck jtag test clock input lvcmos - vddic g3 tdo jtag test data out output lvcmos - vddic j3 sel_2p5v indicate core vdd level, (high = 2.5v, low = 3.3v) input lvcmos - vdd d7 mstrout_en enable all outputs in sync input lvcmos high vdd k9 pll_test2 pll test bit 2 input lvcmos - vddab h4 pll_test1 pll test bit 1 input lvcmos - vddab g5 pll_test0 pll test bit 0 (lsb) input lvcmos - vddcd d5 tpa pll analog test pin output analog - vdda e4 ex_fb_sel select feedback mode (high = external) input lvcmos - vdd c7 vdd control input, status output and core supply power - - vdd a10, b9, c3, c8, g7, h8, j9, k10 vdda analog supply power - - vdda e1 vddab supply for a and b bank outputs power - - vddab h6, j2, k2 vddcd supply for c and d bank outputs power - - vddcd a1, c4, c6 vddic supply for input clocks power - - vddic b2, h3, k1 gnd control input, status output and core ground ground - - gnd a2, b1, b10, c5, d4, d6, e5, e6, f1, f4, f5, f6, f7, g4, g6, h5, j1, k3 table 40. MPC9894 pin listing (continued) signal name description direction type active state supply pin
MPC9894/d 26 timing solutions table 41. MPC9894 pin diagram 12345678910 a vddc gnd qfb qd0 qd1 qc1 qc0 addr0 addr2 vdd b gnd vddic qfb qd0 qd1 qc1 qc0 addr1 vdd gnd c fb_in fb_in vdd vddcd gnd vddcd ex_fb _sel vdd scl sda d clk0 clk0 tms gnd pll_tes t0 gnd sel_ 2p5v mboot int mr e vdda clk1 clk1 tpa gnd gnd media clk_ valid0 clk_ valid1 clk_ valid2 f gnd clk2 clk2 gnd gnd gnd gnd clk_ alarm_ rst pll_ bypass clk_ valid3 g clk3 clk3 tck gnd pll_tes t1 gnd vdd clk_ stat1 clk_ stat0 lock h tdi trst vddic pll_tes t2 gnd vddab preset vdd clk_ stat3 clk_ stat2 j gnd vddab tdo qa0 qa1 qb1 qb0 sel_sta t0 vdd busy k vddic vddab gnd qa0 qa1 qb1 qb0 sel_ stat1 mstrou t_en vdd
MPC9894/d timing solutions 27 MPC9894 programming model table 42. slave address (register 0 ? read only) bit76543210 description not used addr_6 add_r5 addr_4 addr_3 addr_2 read from addr[2] pin addr_1 read from adr[1] pin addr_0 read from addr[0] pin reset default x (tbd) x (tbd) x (tbd) x (tbd) preset default x (tbd) x (tbd) x (tbd) x (tbd) table 43. output configuration register (register 1 ? read/write) bit76543210 description fsel_a[1:0] fsel_b[1:0] fsel_c[1:0] fsel_d[1:0] reset default00000000 preset default00001010 table 44. mode configuration and alarm reset register (register 2 ? read/write) bit76543210 description not used alarm_rst[3:0] (see table 15) idcs_mode[2:0] (see table 16) reset default n/a n/a n/a n/a n/a 0 1 1 preset default n/a n/a n/a n/a n/a 1 0 0 table 45. device configuration and output clock enable register (register 3 ? read/write) bit76543210 description int_e qual_en slew_control enabl e_qfb enable_qa enable_qb enable_qc enable_qd reset default00000000 preset default11001111 table 46. input and feedback divider configuration register (register 4 ? read/write) bit76543210 description reserved reserved res erved reserved input_fb_div[3:0] reset defaultn/an/an/an/a0000 preset defaultn/an/an/an/a0011 table 47. status register (register 5 ? read only) bit76543 2 1 0 description int inverse of int signal clk_stat[3:0] status of clk3, clk2, clk1 and clk0 (sticky) copy of clk_stat[3:0] signal lock inverse of lock signal sel_stat[1:0] copy of sel_stat[1:0] signal table 48. output power-up register (register 6 ? read/write) bit 76543 2 10 description pwr_qd1 pwr_qd0 pwr_qc1 pw r_qc0 pwr_qb1 pwr_qb01 pwr_qa1 pwr_qa0 reset default00000 0 00 preset default11111 1 11 table 49. feedback power-up register (register 7 ? read/write) bit 7 6 5 4 3 2 1 0 description pwr_qfb reset default 0 preset default 1
MPC9894/d 28 timing solutions outline dimensions case 1462-01 issue o date 11/26/02 a1 index area b c 0.2 11 top view 11 4x a1 index area 9x 10 9 8 7 4 3 2 1 a b c d e f g h j k 3 bottom view b m 0.25 c a m 0.10 a 100x 0.55 0.45 6 5 1 0.5 0.5 9x 1 k side view a 0.35 a 0.12 a 100x 0.43 4 (1.18) 1.7 max rotated 90? clockwise detail k seating plane 0.29 5 notes: 1. 2. 3. 4. 5. all dimensions are in millimeters. dimensioning and tolerancing per asme y14.5m, 1994. maximum solder ball diameter measured parallel to datum a. datum a, seating plane, is defined by the spherical crowns of the solder balls. parallelism measurement shall exclude any effect of mark on top surface of packaging. vf suffix 100-lead map bga package case 1462-01 issue o
MPC9894/d timing solutions 29 notes
MPC9894/d 30 timing solutions notes
MPC9894/d timing solutions 31 notes
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